MG2475 > MG2475


MG2475
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The MG2475AZZ-F340C(hereinafter called “MG2475”) is a true 2.4 GHz system-on-chip (SOC) designed for low-power and low-cost applications based on industry standards, IEEE802.15.4 and RF4CE. Some special features and peripherals such as peripherals DMA, memory and I/O retention under the power down modes, etc are added to achieve both enhanced performance and low-power. MG2475 uses an ISM band of 2.4 ~ 2.48 GHz. In addition to the standard 250Kbps data-rate specified in IEEE802.15.4, enhanced high data-rate mode (1Mbps) with channel coding is supported. MG2475 combines an advanced RF transceiver with an industry-standard enhanced 8051 MCU, a baseband PHY, a MAC with AES-128 HW engine, an in-system programmable 64KB flash memory, a 7-KB RAM, and many other application-specific peripherals. For voice applications, the voice encoder/decoder of ADPCM and μ/a-law are embedded. MG2475 fits best for low-cost and low-power RF4CE remote control applications.


[Block Diagram] [Circuit Diagram]

 
RF Transceiver
▶ Integrated 2.4GHz RF Transceiver
▶ Low Power Consumption
▶ High Sensitivity of ?98.5 dBm at 250kbps
▶ No External T/R Switch or Filter needed
▶ On-chip VCO, LNA, and PA
▶ Programmable Output Power up to +9.0dBm
▶ Direct Sequence Spread Spectrum
▶ O-QPSK Modulation
▶ High Data Rate including 250Kbps specified in IEEE802.15.4: 1Mbps
▶ RSSI Measurement
▶ Compliant to IEEE802.15.4

Hardwired MAC
▶ Two 128-byte FIFOs for Modem Tx and Rx
▶ CRC-16 Computation and Check
▶ Address filtering enhanced
▶ Voice MAC header H/W generation

8051-Compatible MCU
▶ 8051 Compatible (single cycle execution)
▶ 64KB Embedded Flash Memory
▶ 7KB Data Memory (support the retention in all power down modes, power-off is possible)
▶ 128-byte CPU dedicated Memory(support the retention in all power down modes, power-off is possible)
▶ 1KB Boot ROM
▶ Dual DPTR Support
▶ 4-channels peripheral DMA(channel 0 is only for MAC RX)
▶ AES-128 Encryption/Decription Engine
▶ ECC(Error Checking and Correction) logic for the Flash or RAM data integrity
▶ I2S/PCM Interface with two 128-byte FIFOs
▶ μ-law/a-law/ADPCM Voice Encoder/Decoder
▶ Two High-Speed UARTs with Two 16-byte FIFOs(up to 1Mbps)
▶ Four Timer/Counters
▶ 5 PWM channels
▶ Watchdog Timer
▶ Sleep Timer using the 32kHz internal RC-OSC
▶ Quadrature Signal Decoder
▶ 22 General Purpose I/Os (support the retention in deep sleep mode)
▶ 16 MHz RC oscillator for the fast start-up from reset & power-down mode
▶ On-chip Power-on-Reset and Brown-out detector
▶ SPI Master/Slave Interface with two 16-byte FIFOs
▶ I2C Master/Slave with 16-byte FIFO
▶ Programmable IR(Infra-Red) Modulator
▶ ISP (In System Programming)
▶ External clock output function(500KHz, 1/2/4/8/16/32 MHz selectable)

Clock Inputs
▶ 32MHz Crystal for System Clock

Power
▶ 1.2V(Core)/2.0~3.6V(I/O) Operation
▶ Power Management Scheme with Deep Sleep Mode
▶ Separate On-chip Regulators for Analog and Digital Circuitry.
▶ Power Supply Range for Internal Regulator(2.0V(Min) ~ 3.6V(Max))

Package
▶ Lead-Free 40-pin QFN Package (6mm x 6mm)